This invention relates to an interconnecting network for use in a parallel computer system in transferring between a processor unit and a memory unit consecutive packets representative of data.
A recent trend in electronic digital computers is to use as a parallel computer system a great number of computer units in parallel. The parallel computer system comprises a plurality of processors collectively as a processor unit and a plurality of memories as a memory unit. Data sequences are bidirectionally transferred between the processor unit and the memory unit through interconnection networks.
In the manner described in an invited paper contributed by Takao Takeuchi and two others to the IEICE Transactions, Volume E 74, No. 4 (April 1991), pages 752 to 760, under the title of "Switch Architectures and Technologies for Asynchronous Transfer Mode", each data sequence is transmitted through an interconnection network as consecutive packets. Various interconnection networks are already known. Each interconnection network has a first plurality of input ports and a second plurality of output ports. The first plurality may be equal to the second plurality.
As will later be described in more detail, the data sequences are supplied to the input ports. Each data sequence comprises a leading packet among the consecutive packets to specify one of the output ports that should be supplied with the data sequence under consideration.
Control buffers are connected to the input ports, respectively, to store the leading packets of the data sequences. Data buffers are connected to the input ports, respectively. Each data buffer stores the leading packet and others of the consecutive packets of the data sequence supplied to one of the input ports that is connected to the data buffer in question. The leading packet and the others of consecutive packets are stored collectively as stored packets. A selector unit is connected to the data buffers and to the output ports to select one of the data buffers that should deliver the stored packets to a certain one of the output ports.
Each of arbiters, equal in number to the control buffers, is connected to the control buffers and to the selector unit. With reference to the leading packets stored in the control buffers to specify one of the output ports in common as a destination port, the arbiters determine one of the data buffers at a time that should deliver the stored packets as output packets to the destination port. In this manner, the arbiters give a priority right for each of the output ports to one of the data sequences to make this one of the data sequences serve as a privileged sequence. The interconnection network serves as a cross-point device operable in machine cycles.
If the privileged sequence and a different sequence of the data sequences are supplied to two of the input ports earlier and later in one machine cycle to have a destination port in common, the selector unit selects the stored packets of the privileged sequence. Having produced these stored packets as the output packets, the selector unit selects the stored packets of the different sequence. If the privileged sequence consists of N consecutive packets, where N represents a natural number, the consecutive packets of the different sequence must be kept in the data buffer therefor during N machine cycles. In this manner, this conventional interconnection network is operable with an unduly long blocking time of overloading the interconnection network. The conventional interconnection network has a low throughput or internal link speed to adversely affect performances of the processor unit and of the parallel computer system.